This invention relates to a vector data processing system which comprises a plurality of vector registers and other circuit or system components related to the vector registers.
Such a vector data processing system is already known. For example, a vector processing system is disclosed in U.S. Pat. No. 4,128,880 issued to Seymour R. Cray, Jr., and assigned to Cray Research, Inc. An information processing device was invented by Hideo Hayashi for use as a vector data processing system. Among patent applications filed in several countries for the information processing device, one filed under the European Patent Convention by NEC Corporation, the assignee of the instant application, is published under Patent Publication No. 0 184 791 A1.
According to Cray, Jr., the vector processing system comprises a plurality of vector registers, a functional unit, such as an adder or a multiplier, a controller, such as an assembly of instruction buffers, an input fan-out for communicating with individual vector registers, and an output fan-out for communicating from any one of the vector registers to the functional unit. The input and the output fan-outs are collectively called a signal path select. According to Hayashi, the information processing device comprises a plurality of vector registers, a functional unit, a controller, a multiplexer connected to the vector registers, and a selector which is also connected to the vector registers. The selector has a function which is somewhat different from the output fan-out of Cray, Jr. At any rate, it is possible to refer to the input fun-out or the multiplexer as a distributor unit, to the output fan-out as a selector unit, and to either the signal path select or a combination of the distributor and the selector of Hayashi as an input/output (I/O) complex.
According to either of Cray, Jr., and Hayashi, the vector data processing system is used in an electronic digital computer comprising a main memory and is operable in compliance with program instructions. Each vector register is for holding a prescribed number of vector elements.
The program instructions may include vector move or transfer instructions. In the manner which will later be described more in detail, a vector move instruction specifies one and another of the vector registers as a source register and a destination register and transfers the vector elements from the source register to the destination register through the input/output complex.
It will later be described in detail that the vector registers are divisible into a predetermined number m of groups, each group comprising a plurality of vector registers. In this event, it is convenient to divide the input/output complex into a plurality of input/output units assigned to the respective groups. Each group may be named a vector data processor. Under the circumstances, each vector data processor comprises a plurality of vector registers, a distributor unit connected to the vector registers, and a selector unit which is also connected to the vector registers. In the manner which will later become clear, division into a predetermined number m of vector data processors is desirable in attaining a high speed for a vector processing operation which is executed in response to at least one of the program instructions.
It should be noted in connection with the foregoing that the vector move instruction should specify one of the vector data processors that includes the destination register and that may or may not be different from the vector data processor including the source register. For this purpose, the vector data processing system may comprise a common distributor between the distributor units of the respective vector data processors and the selector units thereof. Use of such a common distributor, however, adversely affects the high speed as will later become clear.